In many computing and other digital systems, it is necessary to deal with various flows of information and to perform various different processing operations. Dealing with the information flows may require various memories of different speeds and sizes, and performing the processing operations may require one or more processors. The various information paths, memories, and processors need to be coupled together efficiently.
A particular instance of this is in message switching and communication systems where the volume of information passing through a switching node is high. (It will of course be realized that although the invention finds particular application to message switching and communication systems, it is applicable to other systems where similar problems arise.)
The primary design requirement in such systems is to achieve efficient handling of the messages, which involves optimizing the message memory and the information flow paths involving that memory. In addition to the primary functions of receiving, storing, and retransmitting messages, a variety of other functions must also be performed, and a processor is needed to perform these functions. This processor will usually have its own private memory system, for storing its programs and associated data. This processor must, however, be coupled to the rest of the system, so that it can (among other things) read from and write to the main message memory.
The main memory will have its own memory access unit, which will be concerned primarily with achieving efficient message data flow through the main memory. It is convenient to couple the processor to the main memory access unit through a read/write buffer. This enables the main memory controller to interleave access requests from the processor with message information flows, and allows the main memory controller to operate largely independently of the processor, which will normally perform its processing independently of the message flows involving the main memory.
The processor will therefore communicate with the main memory by passing access requests to the buffer. If the access request is a write, then the processor can continue with its processing immediately; the word to be written to main memory will be stored in the buffer and can be ignored by the processor. If the access request is a read, then the processor normally waits until the required word is read from the main memory by the buffer; this involves a wait of typically some 5 to 10 cycles of the processor.
In principle, the processor could be programmed so that on a read, it continues with further operations, not requiring the word being read from the main memory, for a substantial number of cycles, and only then check the buffer for the required word from the main memory. This would reduce the chance of having to wait at all, and even if a wait is required, the wait will generally be short. However, this would normally involve considerable complications in the program, and would also involve at least one cycle for the processor to check the buffer. This technique is therefore not normally employed. Indeed, the architecture of some common processors does not permit this technique: they stall unconditionally on a read.
In many situations, the use of a read/write buffer in this way provides an adequate solution to the problems of coupling the processor to the main memory. The main memory access unit can deal with memory accesses from the processor in such a manner that it does not adversely affect the (more important) message information flows, while the processor can run at close to full speed. The processor loses no cycles for writing to main memory, and although it loses cycles when words have to be read from the main memory, the reads will normally be a small proportion of the processing load and the lost cycles will have only a small impact on the overall speed.
If the information flow rate between the processor and the main memory has to be high, however, there can still be problems.
If a considerable amount of information has to be written from the processor to the main memory, this can usually be achieved without undue difficulty. The buffer can have a capacity of several words, so a block of that number of words can be written into the buffer in whatever manner and rate is most convenient for the processor. If a larger number of words is to be written, then they can usually be stored in the processor's local memory and then transferred block by block to the buffer; this will impose a certain time penalty on the processor, but that penalty will usually be small compared with the processing time required to generate the words in the first place.
If a considerable amount of information has to be read from the main memory to the processor memory, however, the problem can be more severe. For each read call by the processor to the buffer, there is a delay of some 5 to 10 cycles for the desired word to appear in the buffer. While, as discussed above, the processor could be programmed to occupy part of this time by other processing, complicated and careful programming is required, and the processor will use most of the extra processing in repeated switching between generating the successive read calls (and storing their results in the local memory) and whatever other processing task is assigned to it in the intervals between read calls.
The main object of the present invention is to alleviate this problem.
One possible way of tackling the problem is to couple the processor directly to the memory access unit (which normally operates in a direct memory access (DMA) mode). However, this has the disadvantages that the processor is stalled during access to the main memory, and also that the memory access will still normally be subject to delays because the accesses from the processor still have to be interleaved with other memory accesses (for message flows).
Another possible way of tackling the problem is by using a cache system. This also has serious problems. The cache has to be associated with the main memory (the problem is obviously not solved by a cache on the processor side of the buffer, if there is a buffer). For the cache to improve the access speed of the processor to a block of words, transfers between the cache and the main memory should be of a size comparable with the block size. But since the main usage of the main memory is in connection with the message information flows, the main effect of the cache will be on those flows, and this can adversely affect the overall performance.